TLK2201JR |
RFQ for TLK2201JR |
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| Technical/Catalog Information | TLK2201JRGQE |
| Vendor | Texas Instruments |
| Category | Integrated Circuits (ICs) |
| Number of Drivers/Receivers | 1/1 |
| Type | Transceiver |
| Voltage - Supply | 2.3 V ~ 2.7 V |
| Package / Case | 80-BGA MICROSTAR JUNIOR |
| Packaging | Tube |
| Protocol | IEEE 802 |
| Drawing Number | 296; 4200461-4; GQE; 80 |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | TLK2201JRGQE TLK2201JRGQE 296 10486 ND 29610486ND 296-10486 |
| Product | Manufacturers | Pack | D/C |
| TLK2201JR | - | BGA | 04+ |
The TLK2201JR is a member of the transceiver family of multigigabit transceivers, optimized for use with small form-factor optical transceivers that require footprints smaller than 14 mm. The TLK2201JR gigabit ethernet transceiver is fully compliant with IEEE 802.3 requirements for serializer/deserializer functions at 1.25 Gbps. The TLK2201JR supports a wide range of serial data rates from 1.0 Gbps to 1.6 Gbps.
The primary application of this device is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 or 75 . The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The TLK2201JR performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1.0 Gbps of data bandwidth over a copper or optical media interface.
The TLK2201JR supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface with double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (serdes) accepts 10-bit wide 8-bit/10-bit (8b/10b) parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The serdes extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8-bit/10-bit encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first (i.e., bits 04 of the 8-bit/10-bit encoded data) on the rising edge of the clock, and the least significant bits (i.e.,
Features |
| 1.0-to 1.6-Gigabits Per Second (Gbps) Serializer/Deserializer5 mm * 5 mm Footprint Remover Space Limitations With Small Form-Factor Optical TransceiversLow Power Consumption < 250 mW at 1.25 GbpsPECL Compatible Differential I/O on High-Speed InterfaceSingle Monolithic PLL DesignSupport for 10-Bit Interface (TBI) or Reduced Interface 5-Bit Double Data Rate (DDR) ClockingReceiver Differential Input Thresholds 200 mV MinimumIEEE 802.3 (Gigabit Ethernet) CompliantAdvanced 0.25-m CMOS TechnologyInterfaces to Backplane, Copper Cables, or Optical ModulesNo External Filter Capacitors RequiredComprehensive Suite of Built-In TestabilityIEEE 1149.1 JTAG Support2.5-V Supply for Lowest Power Operation3.3-V Tolerant on TTL InputsHot Plug ProtectionESD Protection 2-kV HBM80-Pin 5 mm * 5 mm MicroStar Junior™ BGA |